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DG411/883
Data Sheet June 13, 2008 FN6726.0
Monolithic Quad SPST CMOS Analog Switches
The DG411/883 series monolithic CMOS analog switches are drop-in replacements for the popular DG211 and DG212 series devices. They include four independent single pole throw (SPST) analog switches, and TTL and CMOS compatible digital inputs. These switches feature lower analog ON-resistance (<35) and faster switch time (tON <175ns) compared to the DG211 or DG212. Charge injection has been reduced, simplifying sample and hold applications. The improvements in the DG411/883 series are made possible by using a high voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older CMOS technologies. The 44V maximum voltage range permits controlling 40VP-P signals. Power supplies may be single-ended from +5V to +34V, or split from 5V to 20V. The four switches are bilateral, equally matched for AC or bidirectional signals. The ON-resistance variation with analog signals is quite low over a 15V analog input range. This permits independent control of turn-on and turn-off times for SPDT configurations, permitting "break-before-make" or "make-before-break" operation with a minimum of external logic.
Features
* This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * ON-Resistance <35W Max * Low Power Consumption (PD <35mW) * Fast Switching Action - tON <175ns - tOFF <145ns * Low Charge Injection * Upgrade from DG211/DG212 * TTL, CMOS Compatible * Single or Split Supply Operation
Applications
* Audio Switching * Battery Operated Systems * Data Acquisition * Hi-Rel Systems * Sample and Hold Circuits * Communication Systems
Ordering Information
PART NUMBER DG411AK/883 TEMP. RANGE (C) -55 to +125 PACKAGE 16 Ld CerDIP PKG. DWG. # F16.3
* Automatic Test Equipment
Pinout
DG411/883, (16 LD CERDIP) TOP VIEW
IN1 1 D1 2 S1 3 V- 4 GND 5 S4 6 D4 7 IN4 8 16 IN2 15 D2 14 S2 13 V+ 12 VL 11 S3 10 D3 9 IN3
(NC) NO CONNECTION
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
DG411/883 Functional Diagram
Four SPST Switches per Package Switches Shown for Logic "1" Input
DG411/883 S1 IN1 D1 S2 IN2 D2 S3 IN3 D3 S4 IN4 D4
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SYMBOL IN1 D1 S1 VGND S4 D4 IN4 IN3 D3 S3 VL V+ S2 D2 IN2 DESCRIPTION Logic Control for Switch 1 Drain (Output) Terminal for Switch 1 Source (Input) Terminal for Switch 1 Negative Power Supply Terminal Ground Terminal (Logic Common) Source (Input) Terminal for Switch 4 Drain (Output) Terminal for Switch 4 Logic Control for Switch 4 Logic Control for Switch 3 Drain (Output) Terminal for Switch 3 Source (Input) Terminal for Switch 3 Logic Reference Voltage Positive Power Supply Terminal (Substrate) Source (Input) Terminal for Switch 2 Drain (Output) Terminal for Switch 2 Logic Control for Switch 2
TABLE 1. TRUTH TABLE LOGIC 0 1 NOTE: Logic "0" 0.8V. Logic "1" 2.4V. SWITCH ON OFF
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FN6726.0 June 13, 2008
DG411/883
Absolute Maximum Ratings
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44V GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25V VL (Note 3) . . . . . . . . . . . . . . . . . . . . . . . .(GND -0.3V) to (V+) +0.3V Digital Inputs, VS, VD (Note 4) . . . . . .(V-) -2V to (V+) + 2V or 30mA, Whichever Occurs First Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA Current, S or D (Pulsed 1ms, 10% Duty Cycle) . . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical, Notes 1, 2) JA (C/W) JC (C/W) 16 Ld CERDIP Package. . . . . . . . . . . . 75 20 Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175C Operating Temperature (A Suffix) . . . . . . . . . . . . . .-55C to +125C Storage Temperature Range (A Suffix) . . . . . . . . . .-65C to +125C Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300C
Operating Conditions
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . 20V Max Operating Temperature Range . . . . . . . . . . . . . . . .-55C to +125C Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V Max Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V Min Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20ns
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 3. VIN = Input Voltage to Perform Proper Function. 4. Signals on SX, DX or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
DC Electrical Specifications
Device Tested at: V+ = +15V, V- = -15V, VL = 5V, GND = 0V, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. GROUP A SUBGROUP 1, 3 2 TEMPERATURE (C) +25, -55 +125 LIMITS MIN 0 0 MAX 35 45 UNITS
PARAMETERS Drain-to-Source ON-Resistance
SYMBOL rDS(ON)
CONDITIONS V+ = +13.5V, V- = -13.5V, IS = -10mA, VD = 8.5V VIN = 0.8V V+ = +10.8V, V- = -0V, IS = -10mA, VD = 3.0V and 8.0V VIN = 0.8V
1, 3 2
+25, -55 +125
0 0
80 100

Source OFF Leakage Current
IS(OFF)
V+ = 16.5V, V- = -16.5V, VD = -15.5V, VS = 15.5V VIN = 2.4V V+ = 16.5V, V- = -16.5V, VD = 15.5V, VS = -15.5V VIN = 2.4V
1 2, 3
+25 +125, -55
-0.25 -20
+0.25 +20
nA nA
1 2, 3
+25 +125, -55
-0.25 -20
+0.25 +20
nA nA
Drain OFF Leakage Current
ID(OFF)
V+ = 16.5V, V- = -16.5V, VD = -15.5V, VS = 15.5V VIN = 2.4V V+ = 16.5V, V- = -16.5V, VD = 15.5V, VS = -15.5V VIN = 2.4V
1 2, 3
+25 +125, -55
-0.25 -20
+0.25 +20
nA nA
1 2, 3
+25 +125, -55
-0.25 -20
+0.25 +20
nA nA
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FN6726.0 June 13, 2008
DG411/883
DC Electrical Specifications
Device Tested at: V+ = +15V, V- = -15V, VL = 5V, GND = 0V, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) GROUP A SUBGROUP 1 2, 3 1, 2, 3 1, 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 1 2, 3 TEMPERATURE (C) +25 +125, -55 +25, +125, -55 +25, +125, -55 +25 +125, -55 +25 +125, -55 +25 +125, -55 +25 +125, -55 +25 +125, -55 +25 +125, -55 +25 +125, -55 +25 +125, -55 LIMITS MIN -0.4 -40 -0.5 -0.5 -1.0 -5.0 -1.0 -5.0 -1.0 -5.0 -1.0 -5.0 MAX +0.4 +40 +0.5 +0.5 +1.0 +5.0 +1.0 +5.0 +1.0 +5.0 +1.0 +5.0 UNITS nA nA A A A A A A A A A A A A A A A A A A
PARAMETERS Channel ON Leakage Current
SYMBOL
CONDITIONS
ID(ON) + IS(ON) V+ = 16.5V, V- = -16.5V, VS = VD = 15.5V IIL IIH I+ Input Under Test = 0.8V, All Others = 2.4V Input Under Test = 2.4V, All Others = 0.8V V+ = 16.5V, V- = -16.5, VIN = 0V or 5.0V V+ = 13.2V, V- = 0V, VIN = 0V or 5.0V VL = 5.25V
Input Current with VIN Low Input Current with VIN High Positive Supply Current
Negative Supply Current
I-
V+ = 16.5V, V- = -16.5, VIN = 0V or 5.0V V+ = 13.2V, V- = 0V, VIN = 0V or 5.0V VL = 5.25V
Logic Supply Current
IL
V+ = 16.5V, V- = -16.5, VIN = 0V or 5.0V V+ = 13.2V, V- = 0V, VIN = 0V or 5.0V VL = 5.25V
Ground Current
IGND
V+ = 16.5V, V- = -16.5, VIN = 0V or 5.0V V+ = 13.2V, V- = 0V, VIN = 0V or 5.0V VL = 5.25V
AC Electrical Specifications
Device Tested at: V+ = +15V, V- = -15V, VL = 5V, GND = 0V, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. GROUP A SUBGROUP 9, 11 10 9, 11 10 9, 11 10 9, 11 10 TEMPERATURE (C) +25, -55 +125 +25, -55 +125 +25, -55 +125 +25, -55 +125 LIMITS MIN 0 0 0 0 0 0 0 0 MAX 175 240 250 400 145 160 125 140 UNITS ns ns ns ns ns ns ns ns
PARAMETERS Turn ON Time
SYMBOL tON
CONDITIONS CL = 35pF, VS = 10V, RL = 300 V+ = 12V, V- = 0V, CL = 35pF, VS = +8V, RL = 300
Turn OFF Time
tOFF
CL = 35pF, VS = 10V, RL = 300 V+ = 12V, V- = 0V, CL = 35pF, VS = +8V, RL = 300
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FN6726.0 June 13, 2008
DG411/883
Electrical Specifications
Device Tested at: V+ = +15V, V- = -15V, VL = 5V, GND = 0V, Unless Otherwise Specified. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. GROUP A SUBGROUP 9 TEMPERATURE (C) +25 +25 9 +25 +25 -100 +100 LIMITS MIN -100 MAX +100 UNITS pC pC pC pC
PARAMETERS Charge Injection
SYMBOL Q
CONDITIONS VG = 0V, RG = 0, TA = +25C, CL = 10nF (see Figure 2) VG = 6V, RG = 0, TA = +25C CL = 10nF, V+ = 12V, V- = 0V (see Figure 2)
TABLE 2. ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS Interim Electrical Parameters (Pre Burn-In) Final Electrical Test Parameters Group A Test Requirements Groups C and D Endpoints NOTE: 5. PDA applies to Subgroup 1 only. SUBGROUPS (See "Electrical Spec Tables" on page 3 and page 4) 1 1 (Note 5), 2, 3, 9, 10, 11 1, 2, 3, 9, 10, 11 1
Typical Performance Curves
50 45 40 35 rDS(ON) () 30 25 20 15 60 10 5 0 -20 -15 -10 -5 0 5 DRAIN VOLTAGE (V) 10 30 TA = +25C 15 20 0 -55 -35 -15 5 25 45 65 TEMPERATURE (C) 85 105 125 A: B: C: D: E: F: 5V 8V 10V 12V 15V 20V A 240 210 180 tON, tOFF (ns) B C D E F 150 120 90 tON tOFF V+ = 15V, V- = -15V VL = 5V, VS = 10V
FIGURE 1. ON-RESISTANCE vs VD AND POWER SUPPLY VOLTAGE
FIGURE 2. SWITCHING TIME vs TEMPERATURE
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FN6726.0 June 13, 2008
DG411/883 Typical Performance Curves
40 V+ = 15V, V- = -15V 30 VL = 5V, TA = 25oC 20 10 IS, ID (pA) 0 -10 -20 -30 -40 -50 -60 -15 -10 -5 0 5 10 DRAIN OR SOURCE VOLTAGE (V) 15 100nA 1SW 10nA 10 100 1k 1SW 10k 100k 1M 10M IS(OFF) ID + S(ON) ID(OFF) ISUPPLY 1mA I+, I100A 4SW 10A IL 1A 4SW
(Continued)
100mA 10mA V+ = 15V, V- = -15V VL = 5V
FREQUENCY (Hz)
FIGURE 3. LEAKAGE CURRENT vs ANALOG VOLTAGE
FIGURE 4. SUPPLY CURRENT vs INPUT SWITCHING FREQUENCY
100 80 60 40 Q (pC) Q (pC) CL = 10nF 20 0 -20 -40 -60 -15 -10 -5 0 5 SOURCE VOLTAGE (V) 10 15 CL = 1nF V+ = 15V, V- = -15V VL = 5V
140 120 100 80 60 40 20 0 -20 -40 -60 -15 -10 -5 0 5 DRAIN VOLTAGE (V) 10 15 CL = 1nF V+ = 15V, V- = -15V VL = 5V CL = 10nF
FIGURE 5. CHARGE INJECTION vs ANALOG VOLTAGE (VD)
FIGURE 6. CHARGE INJECTION vs ANALOG VOLTAGE (VS)
Test Circuits
VO is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing edge of the output waveform.
3V LOGIC INPUT 50% 0V
tR < 20ns (10% TO 90% VIN) tF < 20ns (90% TO 10% VIN)
tOFF SWITCH INPUT VS VO SWITCH OUTPUT 0V tON 0.9 VO 0.9 VO
NOTE: Logic input waveform is inverted for switches that have the opposite logic sense. FIGURE 7A.
.
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FN6726.0 June 13, 2008
DG411/883
+5V VL SWITCH INPUT S1 IN1 LOGIC INPUT GND RL V-15V VIN = 3V CL VG VCL V+ D1 +15V SWITCH OUTPUT VO V+ RG D1 VO
Repeat test for all IN and S. For load conditions, see Specifications CL (includes fixture and stray capacitance)
V L V ----------------------------------O = S R +r DS ( ON ) L R
GND
FIGURE 8A.
FIGURE 7B. FIGURE 7. SWITCHING TIME
0V
VO
INX
OFF
ON
OFF
OFF INX
ON Q = VO x CL
OFF
INX dependent on switch configuration input polarity determined by sense of switch. FIGURE 8B. FIGURE 8. CHARGE INJECTION
Burn-In Circuit
1 IN1 2 D1 R1 VC1 D1 3 S1 4 V5 GND 6 S4 7 D4 VA R4 8 IN4
IN2 16 D2 15 S2 14 V+ 13 VL 12 S3 11 D3 10 IN3 9 R4 D3 C3 VL D2 V+ C2 R2
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FN6726.0 June 13, 2008
DG411/883 Typical Schematic Diagram (Typical Channel)
V+
S
VVL
V+ INX D
GND V-
Die Characteristics
DIE DIMENSIONS: 2760m x 1780m x 485 25m METALLIZATION: Type: SiAl Thickness: 12kA 1kA GLASSIVATION: Type: Nitride Thickness: 8kA 1kA WORST CASE CURRENT DENSITY: 1.5 x 105A/cm2
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FN6726.0 June 13, 2008
DG411/883 Metallization Mask Layout
DG411/883
D1 IN1 1 IN2 16 15 D2
2
S1
3
14
S2
V-
4
13
V+ SUBSTRATE
GND
5
12
VL
S4
6
11
S3
7 D4
8 IN4
9 IN3
10 D3
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FN6726.0 June 13, 2008
DG411/883 Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 -A-DBASE METAL b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A) 16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
INCHES SYMBOL A b b1 b2 b3 c c1 MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.840 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 21.34 7.87 2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 16 5.08 1.52 105o 0.38 0.76 0.25 0.038 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94
E
eA
D E e eA eA/2 L Q S1
e
DS
eA/2
c
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 16 0.200 0.060 105o 0.015 0.030 0.010 0.0015
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.
aaa bbb ccc M N
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN6726.0 June 13, 2008

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